Method, apparatus and computer program product for processing stack related exception traps
US6167504A · kind A · utility
5Cited by
6References
35Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 24, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Jul 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of overflow and underflow traps generated during the execution of a program. The invention maintains a predictor value that controls the number of stack elements that are spilled from, or filled to, the top-of-stack cache in response to an overflow trap or an underflow trap (respectively). The predictor reflects the history of overflow traps and underflow traps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.