System for logic extraction from a layout database
US6167556A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Feb 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and process for logic extraction from the layout of logic blocks is described. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout polygon database using techniques in the art. The process comprises processing the transistor level net list in the memory to define groups of transistors according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage and the transistor type. The groups of transistors are analyzed according to their interconnections, and their membership in groups. Finally, logic units are identified in response to the step of analyzing the groups of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.