Method and apparatus for logic synthesis employing size independent timing optimization
US6167557A · kind A · utility
7Cited by
8References
13Claims
0Family size
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Key dates
| Filing date | Apr 28, 1998 |
| Grant date | Dec 26, 2000 |
| Priority date | — |
| Expiry date | Apr 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Size independent timing optimization is performed on an initial circuit design using gain based models for logic cell types. A component library containing various logic elements in a plurality of sizes is provided and a single gain based model for each logic element (cell type) is created therefrom. Initial conditions for gain and delay are then established for each cell type. Gain based optimization, which is size independent, is then performed on the initial circuit design. The optimized size independent solution is then transformed into a realizable discrete circuit solution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.