Method of fabricating a split gate memory cell
US6168995A · kind A · utility
19Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Dec 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
Abstract
A method of fabricating a novel split gate memory cell comprises forming a tunnel oxide layer on a silicon substrate, forming a first conductive layer over said tunnel oxide layer, etching a trench in said conductive layer to divide said conductive layer into two separate layers with a space therebetween, one such layer to become a first gate electrode and the other separate layer to become a floating gate electrode of the device, forming a dielectric layer over the exposed surfaces, and depositing a second conductive layer which will become a second control gate electrode over said dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.