Semiconductor device
US6169299A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
The MOS gate thyristor of the present invention has a p.sup.+ type anode layer (first semiconductor layer), an n.sup.- type base region (second semiconductor layer) with the function of acting as a drift layer, a p.sup.- type base region (third semiconductor layer), and an n.sup.+ type impurity diffusion layer (fourth semiconductor layer) with the function of acting as a source region. On the surface of the base region, an n.sup.+ type floating emitter region (fifth semiconductor layer) is formed, while a first channel region (sixth semiconductor layer) is formed between the impurity diffusion layer and the floating emitter region. At the lower ends of the fourth semiconductor layer and the first channel region an insulation layer is formed. The insulation layer acts to suppress the operation of a parasitic thyristor to ensure a reliable turn-off operation of the transistor. A portion of the semiconductor extends from the n.sup.+ type floating emitter region and lies underneath the insulation layer in the direction alongside the principal plane of the p.sup.+ type anode layer. The extended semiconductor portion helps broaden the carrier injection path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.