Method and apparatus for reducing standby leakage current using a transistor stack effect
US6169419A · kind A · utility
55Cited by
12References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 1998 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Sep 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.