Method and apparatus for implementing predicated sequences in a processor with renaming
US6170052A · kind A · utility
20Cited by
4References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1997 |
| Grant date | Jan 2, 2001 |
| Priority date | — |
| Expiry date | Dec 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus, and methods are disclosed for generating pairs of conditional instructions corresponding to special predicate sequences from single instructions having a predicate. These pairs of conditional instructions update a destination register regardless of the truth or falsity of the predicate. The destination register is renamed to a new physical location. In this manner, register renaming can be used with predicate sequences to gain performance efficiencies and to overcome limitations of the prior attempted approaches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.