Method for forming dual gate oxides on integrated circuits with advanced logic devices

US6171911A · kind A · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventor

• Mo Yu · White Plains, US

Key dates

• Filing date: Sep 13, 1999
• Grant date: Jan 9, 2001
• Expiry date: Sep 13, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

A process for significantly reducing the thickness of and improving the quality and uniformity of a native oxide film which is formed during the formation of MOSFET devices on a silicon wafer in a dual thickness gate oxide process. The native oxide forms on exposed silicon surfaces after selectively etching away regions of a first thicker gate oxide and prior to growing a thinner gate oxide. The thinner gate oxide used to form high performance devices is between about 15 and 50 .ANG. thick. The native oxide which forms on the exposed silicon surfaces has an initial thickness of about 10 .ANG.. After the selective regions have been patterned the wafer is cleaned using a totally HF free cleaning procedure and subjected to a low pressure rapid thermal annealing between about 600 and 1,050.degree. C. in an ambient of H.sub.2 and N.sub.2. The residual oxide thickness is reduced to about 4 .ANG. with an accompanying improvement in thickness uniformity and oxide quality. The residual film is more robust that the initial native oxide and forms a much smaller thickness component of the final thinner gate oxide. After the annealing treatment, the residual native oxide becomes a more robust f…