Method for forming a planar intermetal dielectric using a barrier layer
US6171963A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1998 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Nov 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a planar structure on a semiconductor substrate is disclosed. The method comprises the steps of: forming an interlayer dielectric atop said substrate; patterning and etching said interlayer dielectric, stopping at said substrate, to form a contact opening; forming a barrier metal layer on the bottom and sidewalls of said contact opening and atop said interlayer dielectric; depositing a conducting layer into said contact opening and atop said barrier metal layer; removing a portion of said conducting layer atop said barrier metal layer, leaving a plug in said contact opening; removing a portion of said barrier layer atop said interlayer dielectric; forming a cap barrier layer on exposed portions of said plug, said barrier metal layer, and said interlayer dielectric; and removing a portion of said cap barrier layer atop said plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.