DRAM cell arrangement and method for the manufacture thereof

US6172391A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Bernd Goebel · Dresden, DE
• Emmerich Bertagnolli · Munich, DE
• Helmut Klose · Munich, DE

Key dates

• Filing date: Aug 27, 1998
• Grant date: Jan 9, 2001
• Expiry date: Aug 27, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/519
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An element that prevents the formation of a channel is arranged in a level of the channel region (Kaa) at one of two opposite sidewalls of a semiconductor structure that has a source/drain region (S/D1a) and a channel region (Kaa) of a vertical selection transistor arranged therebelow. The source/drain region as well as a respective word line (W1a) adjoin at both sidewalls. For folded bit lines (B1a), respectively two word lines (W1a) can be formed in the trenches (G2a). The elements of semiconductor structures neighboring along one of the trenches (G2a) are then arranged in alternation at a sidewall of the trench (G2a) and at a sidewall of a neighboring trench (D2a). A storage capacitor can be arranged over a substrate (1a) or can be buried in the substrate (1a). The connection of the selection transistor to a bit line (B1a) can ensue in many ways.