Trenched DMOS device provided with body-dopant redistribution-compensation region for preventing punch through and adjusting threshold voltage
US6172398A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 11, 1997 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Aug 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
This invention discloses a vertical DMOS transistor cell formed in a semiconductor substrate of a first conductivity type with a top surface and a bottom surface. The vertical DMOS transistor cell includes a trenched gate comprising polysilicon filling a trench opened from the top surface disposed substantially in a middle portion of the cell. The DMOS transistor cell further includes a source region of the first conductivity type surrounding the trenched gate near the top surface of the substrate. The DMOS transistor cell further includes a body region of a second conductivity type encompassing the source region. The body region surrounding the trenched gate and extends vertically to about one-half to two-third of the depth of the trenched gate. The body region further includes a body-dopant redistribution-compensation region under the source region near the trenched gate having a delta-increment body dopant concentration distribution higher than remaining portions of the body region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.