Standard cell power-on-reset circuit
US6173436A · kind A · utility
6Cited by
13References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1997 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Oct 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of designing a reset circuit for a digital integrated circuit (IC) layout is described. The reset circuit is designed with the intention of making it visually non-detectable in the digital IC layout by implementing the reset circuit entirely in digital elements and then using standardized digital layout cells and routing such that the reset circuit is essentially non-discernible from the digital circuitry of the IC device layout. In addition, circuit elements are designed using devices having dimensions that are essentially the same as typical digital devices in the digital IC layout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.