Split gate flash memory cell with self-aligned process
US6174771A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 17, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Nov 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method for fabricating split-gate flash memory cells is disclosed. In this method, the field oxide is formed after the formation of the poly-1 stripes, which eventually become the floating gates, by oxide growth, thus, the misalignment problems often encountered in the prior art processes between the floating gates and the field oxide layers are eliminated or at least minimized. The method also includes the step of forming a dummy CVD dielectric sidewall spacer with a predetermined thickness before the formation of the poly-2 layer, which eventually become the control gates; this greatly eliminates or at least minimizes the disparity in the peripheral control gate lengths between mirror (adjacent) cells. Both of these improvements can significantly contribute to the reduction of cell size without involving expensive upgrades in processing equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.