Dual damascene process for capacitance fabrication of DRAM
US6174781A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1999 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Jun 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a capacitor is described in which a substrate comprises a transistor and a planarized insulation layer. An opening is formed in the insulation layer, exposing one of the source/drain of the transistor. A sacrificial plug is formed in the first opening. The insulation layer surrounding the first opening is removed to form a second opening and a certain thickness of the insulation layer is retained at the bottom of the second opening. The sacrificial plug is removed and simultaneously forming a node plug and a first electrode respectively in the first opening and on the bottom and side wall of the second opening. A dielectric layer is further formed on the surface of the first electrode and a second electrode is formed on the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.