Dual damascene manufacturing process
US6174813A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 14, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Oct 14, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7684
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual damascene process of manufacturing dual damascene structure comprising the steps of first providing a semiconductor substrate that already has an insulating layer formed thereon. Next, a trench and a via opening are formed within the insulating layer. In the subsequent step, a first glue layer, preferably a titanium layer, is formed over the trench and the via opening. Thereafter, photolithographic and etching operations are again used to remove a portion of the first glue layer in a region surrounding the trench. Consequently, a portion of the insulating layer is exposed while the trench and the via opening are still covered by the first glue layer. After that, a second glue layer, preferably a titanium nitride layer, is formed over the first glue layer and the insulating layer. Then, a metallic layer is formed over the second glue layer. The metallic layer completely fills the trench and the via opening. The second glue layer and the metallic layer have a polishing selectivity ratio of about 1:1. Finally, a polishing operation is performed to remove a portion of the metallic layer and second glue layer above the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.