Method for providing virtual atomicity in multi processor environment having access to multilevel caches
US6175899A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1997 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | May 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for assuring virtual atomic invalidation in a multilevel cache system wherein lower level cache locations store portions of a line stored at a higher level cache location. Upon receipt of an invalidation signal, the higher level cache location invalidates the line and places a HOLD bit on the invalidated line. Thereafter, the higher level cache sends invalidation signals to all lower level caches which store portions of the invalidated line. Each lower level cache invalidates its portion of the line and sets a HOLD bit on its portion of the line. The HOLD bits are reset after all line portion invalidations have been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.