Demand based sync bus operation
US6175930A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1998 |
| Grant date | Jan 16, 2001 |
| Priority date | — |
| Expiry date | Feb 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register associated with the architected logic queue of a memory-coherent device within a multiprocessor system contains a flag set whenever an architected operation--one which might affect the storage hierarchy as perceived by other devices within the system--is posted in the snoop queue of a remote snooping device. The flag remains set and is reset only when a synchronization instruction (such as the "sync" instruction supported by the PowerPC.TM. family of devices) is received from a local processor. The state of the flag thus provides historical information regarding architected operations which may be pending in other devices within the system after being snooped from the system bus. This historical information is utilized to determine whether a synchronization operation should be presented on the system bus, allowing unnecessary synchronization operations to be filtered and additional system bus cycles made available for other purposes. When a local processor issues a synchronization instruction to the device managing the architected logic queue, the instruction is generally accepted when the architected logic queue is empty. Otherwise the architected operation is retried b…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.