Method of making nonvolatile memory devices having reduced resistance diffusion regions
US6177317A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Apr 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/30
Abstract
A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.