Method of manufacturing salicide layer
US6177319A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Jul 1, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
Abstract
A method of manufacturing a salicide layer is described. A substrate having a memory region and a logic circuit region is provided, wherein the memory region comprises a first gate structure and a first source/drain region and the logic circuit region comprises a second gate structure and a second source/drain region. A first salicide layer is formed on the second gate structure and the second source/drain region in the logic circuit region. A dielectric layer is formed over the substrate. A portion of the dielectric layer is removed to expose the first gate structure and the first salicide layer above the second gate structure. A second salicide layer is formed on the first and the second gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.