Method to form bottom electrode of capacitor
US6177326A · kind A · utility
1Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 1998 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Dec 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/712
Abstract
A method for fabricating a bottom electrode is provided. In this method a dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilicon layer is formed on the dielectric layer and fills the via hole, wherein the cross-section of the patterned doped polysilicon layer is arced or polygonal. The surface of the patterned polysilicon layer is transformed into an amorphous silicon layer. A hemispherical-grain layer is formed on the amorphous silicon layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.