Capacitor in a dynamic random access memory
US6177700A · kind A · utility
3Cited by
1References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A DRAM capacitor. A first dielectric layer is formed over a substrate having a gate and source/drain regions, and a plug penetrating through the first dielectric layer to couple with the source/drain regions. A bottom electrode comprising a vertical pole, a metal plate, a first spacer and a second spacer is formed and contacts with the plug. A second dielectric layer is formed on the bottom electrode, and then a conductive layer is formed on the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.