Method and apparatus for producing a single polysilicon flash EEPROM having a select transistor and a floating gate transistor
US6177703A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 28, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Accordingly, exemplary embodiments of the present invention are directed to single poly flash EEPROM cells which avoid the drawbacks of conventional two poly stacked gate cells, and which are easily integrated with high performance logic technologies. An exemplary two transistor flash-EEPROM memory cell array comprises a plurality of these flash EEPROM cells, each having a select transistor with a bit line and a word line, where the select transistor is in series with a floating gate transistor. The floating gate transistor has a thin tunneling oxide formed on a textured monocrystalline substrate. The floating gate is also formed over a heavily doped region in the substrate which forms a coupling line capacitively coupled to the floating gate, and which performs a tunneling function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.