Integrated circuit package and flat plate molding process for integrated circuit package
US6177723A · kind A · utility
38Cited by
21References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package having a top opening and a cavity, with a chip adhered in the cavity. The top opening has routing strips electrically connecting the top opening with the outer surface. The routing strips are electronically connected to bonding pads located in a central area of the chip. Following assembly of the components, the top opening and the cavity are encapsulated in a molding process. A method is provided for forming a substantially flat integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.