Semiconductor memory device having Y-select gate voltage that varies according to memory cell access operation
US6178136A · kind A · utility
32Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic random access memory (DRAM) includes a Y-select circuit (218) that connects a pair of bit lines (204a and 204b) to a pair of sense nodes (210a and 210b). The Y-select circuit (218) provides a first impedance in a read operation, and a second impedance that is lower than the first impedance, in a write operation. Changes in Y-select circuit (218) impedance are achieved by driving transistors (N210a and N210b) within the Y-select circuit (218) with a first voltage during a read operation, and a second voltage during a write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.