Asynchronously addressable clocked memory device and method of operating same
US6178138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 1999 |
| Grant date | Jan 23, 2001 |
| Priority date | — |
| Expiry date | Sep 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing circuit produces a clock signal. An address buffer circuit receives and stores a first address in a first latch and a second address in a second latch asynchronously with respect to the clock signal. A memory control circuit associated with an array of memory cells accesses a first memory cell in the array corresponding to the first address in a first clocked access cycle, and accesses a second memory cell in the array corresponding to the second address in a second clocked access cycle. If a further address is asynchronously received before said second access cycle, the further address replaces the second address in the second latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.