Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K DRAMS using disposable-oxide processing
US6180446A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 1998 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Dec 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A capacitor structure and method. The capacitor (12) comprises a HDC dielectric (40) and upper (44) and lower electrodes. The lower electrode comprises a capacitor via (19), diffusion barrier (34) and an oxygen stable material (36). The diffusion barrier (34) is formed over the capacitor via (19) and bitline via (17). The bitline structure (20) is then formed. Next, a multi-level dielectric (80,84) is formed and storage node areas (70)are etched through the multi-level dielectric leaving dielectric sidewalls (66) on the bitline structure (20). The oxygen stable material (36) is then formed in the storage node area (70). Portions of the multi-level dielectric layer (84) over the bitline structure (20) are removed. The HDC dielectric (40) is then formed adjacent the oxygen stable material (36).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.