Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squared

US6180453A · kind A · utility

Assignee

• VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION · TW

Inventors

• Janmye Sung · Taipei, TW
• Chih-Yuan Lu · Taipei, TW

Key dates

• Filing date: Dec 21, 1998
• Grant date: Jan 30, 2001
• Expiry date: Dec 21, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A process for fabricating a DRAM cell, with an area equal to five times the minimum feature, squared, (5F.sup.2), has been developed. The process features the use of selectively formed, N+ single crystalline, silicon plugs, on underlying source/drain regions. The N+ single crystalline, silicon plugs, epitaxial deposited, are used to connect overlying crown shaped capacitor structures, to underlying source/drain region, as well as to connect a bit line metal structure, to another source/drain region.