Method of producing a memory cell configuration

US6180458A · kind A · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Wolfgang Krautschneider · Ottobrunn, DE
• Franz Hofmann · Munich, DE
• Wolfgang Roesner · Austin, US

Key dates

• Filing date: Jun 10, 1998
• Grant date: Jan 30, 2001
• Expiry date: Jun 10, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

A memory cell configuration includes first memory cells with planar MOS transistors and second memory cells with vertical MOS transistors. The planar MOS transistors are disposed on the bottom of and on the crown of parallel, strip-like trenches. The vertical MOS transistors are disposed on the side walls of the trenches. The memory cell configuration can be produced with a mean area requirement for each memory cell of 1 F.sup.2, where F is the minimum structure size.