Method of fabricating field effect transistor with silicide sidewall spacers
US6180477A · kind A · utility
11Cited by
7References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 16, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Apr 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a field effect transistor is described. A gate oxide layer is formed on a substrate. A gate is formed on the gate oxide layer. A source region and a drain region are formed beside the gate in the substrate. A first spacer is formed beside a sidewall of the gate. A preserve layer is formed beside the first spacer. A second spacer is formed beside a sidewall of the preserve layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.