Fabrication process for a single polysilicon layer, bipolar junction transistor featuring reduced junction capacitance
US6180478A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Apr 19, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/421
Abstract
A process for fabricating a bipolar junction transistor, (BJT), featuring reduced junction capacitance, resulting from the decreased dimensions of extrinsic, and intrinsic base, regions, has been developed. The BJT device, is comprised with only a single polysilicon level, used for the emitter structure, while an extrinsic base, and intrinsic base region, are accommodated in an epitaxial silicon layer, grown on an underlying silicon, active device region, and grown on a silicon seed layer, which in turn overlays insulator isolation regions. A boron doped, intrinsic base region can be formed in an undoped version of the epitaxial silicon layer, or the boron doped, intrinsic base region can be contained in the as deposited, epitaxial silicon layer, or contained in an as deposited, epitaxial, silicon-germanium layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.