Method for forming planarized multilevel metallization in an integrated circuit
US6180509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53233
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming planar multilevel metallization of a semiconductor integrated circuit, and an integrated circuit formed according to the same. Multilevel metallization is achieved through a planar process at each layer to allow for minimum widths of lines and vias and minimal lateral spacing between lines. Conductive lines and contacts are formed before planarization to further achieve good step coverage. A first metallization layer is formed by depositing aluminum over the integrated circuit, patterning and etching to form metal interconnect lines. Regions of planar insulating material are then formed between the metal lines. Another layer of aluminum is deposited and etched to form metal vias over selected portions of the metal lines. This layer of aluminum is patterned with a reverse pattern of that used to pattern the metal lines. Again, regions of planar insulating material are formed between the metal vias. The process of forming the aluminum lines and vias before planarization is free of voids, provides good step coverage and minimizes electromigration problems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.