Depletion strap semiconductor memory device
US6180975A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/373
Abstract
A memory cell structure which uses field-effect controlled majority carrier depletion of a buried strap region for controlling the access to a trench-cell capacitor is described. The buried strap connection between the trench capacitor and the bitline contact in regions where the deep trench pattern intersects the active area of the device. The upper section of the trench contains a single crystalline material to minimize the amount of leakage. The memory cell structure includes a field-effect switch having a gate terminal which induces the depletion region in the substrate and the top of the trench, the extent of the depletion region varying as a function of a voltage applied to the gate terminal; a storage device that includes an isolation collar and a capacitor, the depletion region overlapping the isolation collar when the field-effect switch is in an off-state, and the depletion region does not overlap the isolation collar when the field effect switch is in an on-state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.