Memory cell arrangement with vertical MOS transistors and the production process thereof

US6180979A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Franz Hofmann · Munich, DE
• Josef Willer · Riemerling, DE
• Wolfgang Krautschneider · Ottobrunn, DE

Key dates

• Filing date: Sep 8, 1998
• Grant date: Jan 30, 2001
• Expiry date: Sep 8, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

In a memory cell arrangement which has vertical MOS transistors as memory cells, the information is stored by different threshold voltages of the transistors. For this purpose, dopant regions are formed for an information state by angled implantation or outdiffusion in the upper region of the channel region. The lower region of the channel region is in this case covered by an etching residue (9') which is formed by masked spacer etching. The arrangement can be produced with an area requirement for each memory cell of 2 F.sup.2 (F: minimum structure size).