Integrated passive devices with reduced parasitic substrate capacitance
US6180995A · kind A · utility
31Cited by
7References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 6, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | May 6, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming high quality inductors and capacitors in semiconductor integrated circuits utilizes one or more sealed air-gaps in a supporting substrate under the passive devices. The process is compatible with standard silicon processing and can be implemented with high temperature processing at the beginning, middle, or end of an integrated circuit fabrication process. A one micron air-gap in a high resistivity epitaxial layer results in a parasitic capacitance equivalent to 3.9 micron thick silicon oxide or a 11 micron thick depletion layer in silicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.