Method and apparatus for a RAM circuit having N-Nary output interface
US6181596A · kind A · utility
13Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1999 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Dec 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-NARY, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-NARY, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-NARY) 1-of-N logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.