Method and system for automatic synchronous memory identification
US6182253A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 1997 |
| Grant date | Jan 30, 2001 |
| Priority date | — |
| Expiry date | Jul 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A time conserving method of identifying width, depth, access time, control line configurations, and part type of any of a plurality of different synchronous memories. A nested loop process is used to develop, and apply to a synchronous memory being identified, trial control line configurations taken from ordered entries of tables representative of the plurality of synchronous memories. The width, depth, control line configurations, and part type are determined from the responses evoked from the synchronous memory being identified. The delay between a read command issued by the test system CPU and a reading of bit patterns from the synchronous memory is incremented in finite steps in successive write/read iterations until the bit pattern read is identified to the bit pattern written into the synchronous memory, thereby identifying the access time of the synchronous memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.