Process for forming a high-K gate dielectric
US6184072A · kind A · utility
121Cited by
7References
2Claims
0Family size
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Key dates
| Filing date | May 17, 2000 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | May 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO.sub.2 or a combination of SiO.sub.2, SiO.sub.3 and SiO.sub.4 (oxide-nitride or oxynitride) stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.