Method of implementing differential gate oxide thickness for flash EEPROM
US6184093A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 21, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Aug 21, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/981
Abstract
Improved methods for fabricating semiconductor integrated circuit devices, in particular flash EEPROM devices. According to an embodiment, the present invention provides a method of forming a semiconductor device having a gate oxide layer (120) that is thin in some regions, such as the cell region, and thicker in other regions (155), such as the periphery region. The method provides the gate oxide layer with different thicknesses without the thickness control problems of prior art methods that use contaminant-containing photoresist with an etching step. According to the present invention, the gate oxide has a first thickness that is sufficiently thin to provide high driving capability for the semiconductor device, and a second thickness that is sufficiently thick to provide high voltage reliability of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.