Capacitor trench-top dielectric for self-aligned device isolation
US6184107A · kind A · utility
24Cited by
3References
7Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Mar 17, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Mar 17, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/0383
Abstract
A semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. A deep trench fill fills each deep trench. A buried strap extends completely across each deep trench over each deep trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.