Method of fabricating self-aligned silicide
US6184115A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is directed towards a method of fabricating a self-aligned silicide on gate electrode and source/drain region of a semiconductor device. A semiconductor substrate having gate oxide layer and polysilicon layer is provided. Next, a first silicide layer is formed on polysilicon layer. The substrate is patterned and then, etched to form a gate structure. A spacer is formed on the sidewall of the gate structure and source/drain region is formed adjacent thereto. A metal layer is covered on the surface of the substrate. The substrate is performed a thermal process to convert the portion of the metal layer on gate structure and source/drain region into self-aligned silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.