Low resistivity poly-silicon gate produced by selective metal growth
US6184129A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Sep 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/488
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a low resistivity polymetal silicide conductor/gate comprising, the steps of forming a polysilicon (66) over a gate oxide (64) followed by protection of the polysilicon (66) with a sacrificial material (68), is disclosed. Gate sidewalls (70) are created to protect the sides of the polysilicon (66) and the sacrificial material (68), followed by stripped the sacrificial material (68) to expose the top surface of the polysilicon (66). Next, a diffusion barrier (76) is deposited over the exposed polysilicon (66) and a metal layer (78) is selectively grown on the diffusion barrier (76) to form a gate contact and conductor. Finally, a dielectric layer (80) is deposited over the selectively grown metal layer (78), the sidewalls (70) and the gate oxide (64).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.