Method for forming a ultra-thin gate insulator layer
US6184155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2000 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Jun 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming an ultra-thin, silicon dioxide, gate insulator layer, for narrow channel length MOSFET devices, has been developed. The process features the use of a two step, in situ steam generated, (ISSG), procedure, to grow a silicon dioxide layer at a physical thickness between about 10 to 20 Angstroms, offering a gate insulator layer with a reduction in leakage current, during standby, or operating modes, when compared to counterpart silicon dioxide layers, formed without the use of the two step, ISSG procedure. The two step, ISSG procedure is comprised of a first step, featuring a steam oxidation, and an in situ anneal, in a nitrous oxide ambient, followed by the second step of the two step, ISSG procedure, performed in situ, in the same furnace used for the first step of the two step, ISSG procedure, with the second step of the two step, ISSG procedure again comprised of a steam oxidation, followed by an in situ anneal, performed in a nitrous oxide ambient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.