I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection

US6184557A · kind A · utility

Assignee

• NATIONAL SEMICONDUCTOR CORPORATION · US

Inventors

• Pavel Poplevine · Foster City, US
• Alexander Kalnitsky · San Francisco, US
• Hengyang (James) Lin · San Jose, US
• Albert Bergemont · Palo Alto, US

Key dates

• Filing date: Jan 28, 1999
• Grant date: Feb 6, 2001
• Expiry date: Jan 28, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/911

Abstract

The n-channel and p-channel driver transistors of an I/O circuit are electrostatic discharge (ESD) protected by utilizing a pair of well structures that resistively delay an ESD event from reaching the driver transistors, and that form diodes that direct the ESD event to the supply rail or ground of the circuit.