Low impact signal buffering in integrated circuits
US6184711A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | May 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low impact buffer structure disposed in unused silicon area in a signal line routing channel between logic cell rows of an integrated circuit. In a buffer cell according to the invention, power to the buffer is provided by the power supply rails of one or more nearby logic cell rows. Both the connections to the supply rails and the connections between the transistors of the buffer cell are constructed of a polysilicon material and/or lower metal layer. In this manner, the buffer cell does not significantly impact the routing of metal signal lines in the signal line routing channel. In addition, the buffer cells can be arranged in a "staggered" configuration wherein separate buffers are provided in individual routing tracks of a signal line routing channel, further reducing the possibility of interference with normal signal routing. In addition, layout and routing tools according to the present invention are capable of monitoring the routing or loading of a signal line to determine when it reaches a length or load factor that may give rise to timing problems. When such a signal line is identified, the routing tool routes the signal line to the nearest available buffer cell or caus…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.