General purpose decode implementation for multiported memory array circuits
US6185148A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2000 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Feb 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Among other things, the present invention provides an improved decoder section with a noise resistant input. In one embodiment, the section includes a ratioed gate and a stack with at least one transistor. The ratioed gate has an input for receiving a first input signal, which may be noisy, from one or more input signals and an output that generates a true value, when the gate is activated, if the first input signal is true. The stack with at least one transistor is operably connected to the ratioed gate. It has at least one input for receiving the remaining one or more input signals apart from the first input signal. When these remaining input signals are true, the stack activates the ratioed gate. Otherwise, if any of the remaining signals are false, it inactivates the gate. Accordingly, the ratioed gate generates a true output when all of the one or more inputs are true.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.