Clock-synchronous system
US6185150A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 1999 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Nov 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay circuit produces an activation signal by delaying a clock signal by 270 degrees. A receiver circuit is responsive to the activation signal to capture a command latch enable signal indicating a command cycle and produce an internal signal corresponding to the command cycle. An AND circuit produces a command latch signal synchronized with the clock signal during an interval in which the internal signal is produced. Command receivers take command-forming signals only when the command latch signal is applied thereto. That is, these command receivers are activated only when the command latch signal is received but not at all times. This prevents power dissipation from increasing and allows a plurality of signals to be monitored reliably.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.