Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time
US6185629A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 1994 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Mar 8, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is a data processing apparatus which may interface with plural types of memories. A static decoder coupled to an external port decodes signals which from an external source that indicate the type of memory. Interface circuitry receives coded information from the static decoder and selects a protocol for information transfer. In the preferred embodiment, the protocol includes addressing information having multiplexed row/column addresses for accessing dynamic memories or un-multiplexed addresses for accessing static memories. The interface circuitry further includes a column address shifter. The column address shifter shifts address bits to vary the number of bits available for column addressing. The data processing apparatus attempts to use page mode addressing whenever possible. A lastpage register coupled to the address generator for stores previous address information. A comparator compares the previous address information stored in the lastpage register to the current address. If no page change is detected, the data processor supplies only the column address to the memory in a page mode cycle, or else the data processor supplies a full new address including both …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.