Memory system including a plurality of memory devices and a transceiver device
US6185644A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2000 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Jan 19, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having a master device and a plurality of memory subsystems, including first and second memory subsystems coupled to a first bus. Each memory subsystem includes a plurality of memory devices. The master device transmits a request for a read operation onto the first bus to access data from at least one memory device included in at least one memory subsystem. The first and second memory subsystems each include a transceiver device, a bus, and first and second memory devices. Each transceiver device connects to the first bus. The bus of each memory subsystem connects to each respective transceiver device, wherein each transceiver device is coupled between the first bus and each respective memory subsystem bus. The first and second memory devices in each memory subsystem are coupled respective transceiver devices via respective buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.