Chip performance optimization with self programmed built in self test
US6185712A · kind A · utility
30Cited by
14References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Jul 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) chip wherein a built-in self test determines the IC's optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon each chip power-up, the optimum performance setting is retrieved and provided to chip control which sets the chip for its best performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.