Method and apparatus for improving stuck-at fault detection in large scale integrated circuit testing
US6185713A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 1998 |
| Grant date | Feb 6, 2001 |
| Priority date | — |
| Expiry date | Apr 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A bus holder for coupling to an integrated circuit bus driven by a plurality of tri-state devices. The bus holder has a bidirectional port and first and second test ports. Logic circuitry coupled between the respective ports is configured such that application of a logic 0 to the first test port causes the bidirectional port to drive whatever logic value is applied to that port; application of a logic 1 to the first test port and application of a logic 0 to the second test port pulls the bidirectional port down to a logic 0; and, application of a logic 1 to both the first and second test ports pulls the bidirectional port up to a logic 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.